LS1043ARDB SerDes RCW 协议参考
下面只列举了我感兴趣的部分，建议参考官方文档。
温馨提示：本笔记内容是英文的
参考文献
Reference: Layerscape® 1043A | NXP （https://www.nxp.com.cn/products/LS1043A）
原文内容（部分）：
SerDes protocols
The following table shows the supported protocol options for the SerDes module. The following notation conventions are used in the table:
• SGMII notation for frame manager (FMan):
• sg.mn means SGMII (1 lane @ 1.25 Gbps or 3.125 Gbps)
• “m” indicates that MAC is from FMan.
• “n” indicates which MAC on the FMan.
• For example, “sg.m9,” indicates SGMII for MAC 9 on FMan.
• QSGMII notation for frame manager (FMan)
• XFI notation for FMan:
• xfi.mn means XFI (1 lane @ 10.3125 Gbps)
• “m” indicates that MAC is from FMan.
• “n” indicates which MAC on the FMan.
• For example, “xfi.m9,” indicates XFI for MAC 9 on FMan.
• PCI Express :
• PEXn (5/2.5) means PCI express operating up to 5 or 2.5 Gbps depending on maximum rate selection and training.
• SATA
• SATAn (6/3/1.5) means SATA operating at 6 or 3 or 1.5 Gbps depending on rate selection. The rate of selection is performed by PxSCTL[SPD] register as described in SATA 3.0.
Supported SerDes options（Reference）
| SRDS_PRTCL_S1 RCW[128:143] (hex) | A | B | C | D | PLL Mapping |
|---|---|---|---|---|---|
| 0000 | UNUSED | UNUSED | UNUSED | UNUSED | UNUSED |
| 1555 | xfi.m9 | PCIe 1 (x1) | PCIe 2 (x1) | PCIe 3 (x1) | 1222 |
| …… | …… | …… | …… | …… | …… |
| 4558 | qs.m1,2,5,6 | PCIe 1 (x1) | PCIe 2 (x1) | SATA | 2221 |
| …… | …… | …… | …… | …… | …… |
| 3358 | sg.m9 | sg.m2 | PCIe 2 (x1) | SATA | 2221 |
| 3558 | sg.m9 | PCIe 1 (x1) | PCIe 2 (x1) | SATA | 2221 |
| …… | …… | …… | …… | …… | …… |
SerDes lane assignments
The following table shows the SerDes lanes correspond to the SD1_TXn_P/N and SD1_RXn_P/N signals
| Lane A | Lane B | Lane C | Lane D |
|---|---|---|---|
| SD1_RX0_P | SD1_RX1_P | SD1_RX2_P | SD1_RX3_P |
| SD1_RX0_N | SD1_RX1_N | SD1_RX2_N | SD1_RX3_N |
| SD1_TX0_P | SD1_TX1_P | SD1_TX2_P | SD1_TX3_P |
| SD1_TX0_N | SD1_TX1_N | SD1_TX2_N | SD1_TX3_N |
Frame manager MACs
Each FMan supports seven MACs. These MAC’s support different protocols as summarized in the table below.
| MAC | RGMII 1 Gbps | SGMII 1 Gbps | SGMII 2.5 Gbps | XFI 10 Gbps |
|---|---|---|---|---|
| 1 | - | Y | - | - |
| 2 | - | Y | Y | - |
| 3 | Y | - | - | - |
| 4 | Y | - | - | - |
| 5 | - | Y | - | - |
| 6 | - | Y | - | - |
| 9 | - | Y | Y | Y |
Default FMAN Configuration
See: u-boot/include/configs/ls1043ardb.h
#ifndef SPL_NO_FMAN
#define AQR105_IRQ_MASK 0x40000000
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define QSGMII_PORT1_PHY_ADDR 0x4
#define QSGMII_PORT2_PHY_ADDR 0x5
#define QSGMII_PORT3_PHY_ADDR 0x6
#define QSGMII_PORT4_PHY_ADDR 0x7
/* The AQR PHY model and MDIO address differ between board revisions */
#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */
#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
#endif
Disabling unused SerDes modules
In order to disable the SerDes1 module, the following should be configured:
• SRDS_PLL_PD_S1 = 2’b11 (both PLLs configured as powered down)
• SRDS_PLL_REF_CLK_SEL_S1 = 2’b00
• SRDS_PRTCL_S1=0x0000 (no other values are permitted when both PLLs are powered down)
The powerdown of SerDes data lanes can be achieved by software using registers in the SerDes control block. Refer RCW[SRDS_PLL_PD_S1] bit definition to see how lanes can be powered down based on the powering down of individual PLLs.
Valid SerDes RCW Encodings and Reference Clocks
| SerDes protocol (given lane) | Valid reference clock frequency | Valid setting for | SRDS_PRTCL_SnValid setting for SRDS_PLL_REF_CLK_SEL_Sn | SRDS_PRTCL_SnValid setting for SRDS_PLL_REF_CLK_SEL_Sn | Valid setting for SRDS_DIV_*_Sn |
|---|---|---|---|---|---|
| - | - | - | PLL1 | PLL2 | - |
| PCI Express 2.5 Gbps (doesn’t negotiate upwards) | 100 MHz | Any PCIe | 0: 100 MHz | 0: 100 MHz | 10: 2.5G |
| 125 MHz | Any PCIe | 1: 125 MHz | 1: 125 MHz | 10: 2.5G | |
| …… | …… | …… | …… | …… | …… |
| SATA (1.5, 3, 6Gbps) | 100 MHz | Any SATA | 0：100 MHz | - | Don’t Care |
| 125 MHz | Any SATA | 1: 125 MHz | - | Don’t Care | |
| …… | …… | …… | …… | …… | …… |
怎么看上面这些个玩意呢，简单说明一下（其实官方的上面的介绍已经说了，只不过是英文的）：
左边的RCW(HEX)提供了功能组合选配，对应的功能是A、B、C、D，PLL对应了ABCD的时钟频率
另外，我们只能从已有的RCW选择配置